c++ - What is L1/L2 cache behavior for LUTs and the alike? -

assuming lut of 512kb of 64-bit double types. speaking, how cpu cache structure in l1 or l2?

for example: access middle element, attempt cache whole lut or of - middle element , n subsequent elements?

what kind of algorithms cpu use determine keeps in l2 cache? there look-ahead strategy follows

note: i'm assuming x86, i'd interested in knowing how other architectures works power, sparc etc..

it depends on data structure use lut (look-up table?)

caches @ best things laid out contiguously memory (e.g. arrays or std::vectors) rather scattered around.

in simple terms, when access memory location, block of ram (a "cache line" worth -- 64 bytes on x86) loaded cache, possibly evicting previously-cached data.

generally, there several levels of cache, forming hierarchy. each level, access times increase capacity.

yes, there lookahead, limited rather simplistic algorithms , inability cross page boundaries (a memory page typically 4kb in size on x86.)

i suggest read what every programmer should know memory. has lots of great info on subject.