gnu make - Dependencies in Makefiles -

suppose have makefile:

all: $(binary)  $(binary): $(objs) $(debug_objs)     #link objects here  $(objs): headers     #compile code objects without debug option  $(debug_objs): headers     #compile code objects debug option  headers:     #create on-the-fly header files 

as can see, target headers required both $(objs) , $(debug_objs). question is, headers called twice? also, below code equal/equivalent above:

all: $(binary)  $(binary): headers $(objs) $(debug_objs)     #link objects here  $(objs):      #compile code objects without debug option  $(debug_objs):      #compile code objects debug option  headers:     #create on-the-fly header files 

in that, headers called before $(objs) , $(debug_objs) $(binary)?

no, headers done once.

you can write simple makefile test it:

all: foo bar  foo: baz  bar: baz  baz:         echo 'hi' 

on doing make, hi echoed once.

and in 2nd case make sees $(binary) depends on headers first, goes , headers before other dependencies.