vhdl - Modelsim: how to setup 27 MHz clock -

i want setup 27 mhz clock signal in modelsim. setup clock right clicking signal -> clock -> setup period. example, 50 mhz clock -> 20 ns or used force statement.

because 27 mhz clock special, not integer period, if setup clock appx value, having timing issues.

so, how setup clock?

your clocks asynchronous. will have "timing issues" - if 2 clock edges come close each other (as inevitably sometimes) of flops exhibit metastability.

you need resynchronise 27 mhz domain signals 50 mhz domain, accept , mitigate fact synchronisation wrong. there techniques reduce value of "occasionally" small value think appropriate system, you'll never rid of it.

see fpga-faq 0017, tell me metastability.