synthesis - Is $readmem synthesizable in Verilog? -

i trying implement microcontroller on fpga, , need give rom program. if use $readmemb, correctly synthesized rom? if not, standard way this?

i amend george's answer depends on synthesis tool whether or not $readmemb synthesizable.

altera's recommended hdl coding styles guide includes example 10-31 (page 10-38), demonstrates rom inferred $readmemb (reproduced below):

module dual_port_rom (    input [(addr_width-1):0] addr_a, addr_b,    input clk,     output reg [(data_width-1):0] q_a, q_b );    parameter data_width = 8;    parameter addr_width = 8;    reg [data_width-1:0] rom[2**addr_width-1:0];    initial // read memory contents in file            // dual_port_rom_init.txt.     begin       $readmemb("dual_port_rom_init.txt", rom);    end    @ (posedge clk)    begin       q_a <= rom[addr_a];       q_b <= rom[addr_b];    end endmodule 

similarly, xilinx's xst user guide states that:

the $readmemb , $readmemh system tasks can used initialize block memories. more information, see:

initializing ram external file coding examples

use $readmemb binary , $readmemh hexadecimal representation. avoid possible difference between xst , simulator behavior, xilinx® recommends use index parameters in these system tasks. see following coding example.

$readmemb("rams_20c.data",ram, 0, 7);