arrays - How to use a variable list as a target in a Makefile? -

suppose working on makefile , have following variable declaration @ top:

files = file1.cpp file2.cpp file3.cpp

now suppose want compile each of special command without specifying each target this:

file1.o : file1.cpp     custom_command file1.cpp file2.o : file2.cpp     custom_command file2.cpp file3.o : file3.cpp     custom_command file3.cpp

is there better way using $(files) variable declared above?

something like:

$(files:.cpp=.o) : $(files)     custom_command $(files)

...only needs each file in $(files) variable.

yes. there known pattern rules. example easiest understand:

%.o: %.cpp        $(cc) -c $(cflags) $(cppflags) $< -o $@

(remember makefiles require tabs). rule describes how make object file cpp file.

if not want such broad rule, can use called static patterns:

objects = file1.o file2.o file3.o  all: $(objects)  $(objects): %.o: %.cpp         $(cc) -c $(cflags) $(cppflags) $< -o $@

here's section on static pattern rules , pattern rules in gnu make manual.

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