vhdl - How is a variable shown in a RTL viewer in Quartus? -

how variable depicted in rtl viewer in quartus. open rtl viewer , not show register variable.

for example:

variable op_code   : std_logic_vector(7 downto 0); 

is there reason why rtl viewer not show op_code in rtl viewer? using vhdl.

edit:

op_code(7 downto 0) <=instr_reg(31 downto 24);  if ( op_code = add or op_code = mysub) <br>     c_addr <= instr_reg(14 downto 10); <br> end if;               case op_code(7 downto 0)     --some case statments end case; 

has been optimised away? if elements of opcode used other things, may have been subsumed other logic , not visible in own right anymore.

another thought - if haven't described behaviour of register (which variable comes down reading before writing in clocked process) no register created. it'll combinatorial logic within process, , combined other things. maybe post whole process (or bit more of it) - might able more way.